In the field of semiconductor device manufacturing, a semiconductor device such as, for example, a transistor or more specifically a complementary metal-oxide-semiconductor (CMOS) field-effect-transistor (FET) is normally manufactured or fabricated by well-known front end of line (FEOL) technologies. After the semiconductor device is formed, normally either tensile or compressive stress is induced into a channel region of the device, for example, by applying or depositing a dielectric stress liner covering the top of the semiconductor device. Introduction or induction of stress to the channel region of the device improves performance of the device by causing increased mobility of electronic charges, including electrons and/or holes, in the channel region.
As is well-known in the art, in order to improve the effectiveness of stress liners applied to a transistor, sidewall spacers of the transistor may be removed or at least partially removed (thin-down), before the stress liner is applied such that the stress liner may be disposed close enough to the channel region of the transistor, inducing bigger stress therein and achieving better performance. Following the application of the stress liner, one or more conductive studs may be subsequently created to provide electrical connections to contact areas of the source, drain, and/or gate regions of the transistor. Contacts to the source and/or drain regions are normally formed in silicided areas of the source/drain regions, adjacent to the source/drain extension regions of the transistor. Silicided areas of the source/drain regions may be silicided polysilicon, for example, nickel silicide (NiSi) for improved conductivity.
With continued scaling down in semiconductor device dimensions, source/drain regions of a transistor are becoming increasingly smaller, and thus contact areas thereupon are becoming more closer to source/drain extension regions, which are next to the gate region of the transistor. Consequently, source/drain extension regions are becoming more vulnerable to potential contact punch-through, sometimes also known as “over-etch”, due to for example possible misalignment of openings in a process of forming contacts through conductive studs.
Therefore, there exists the need in the art to broaden process windows of forming conductive studs contacting source/drain regions of semiconductor devices such as transistors without causing punch-through or over-etch to adjacent source/drain extension regions.